Senior Silicon Design Verification Engineer, YouTube Video Accelerators

Role Overview

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a part of the Design Verification (DV) role in the Argos IP team, you will ensure the functional correctness of custom video codec ASICs for YouTube by managing a specialized High-Level Synthesis (HLS) workflow that requires verification at both the C/C++ and RTL levels. You will be responsible for bridging the gap between algorithmic intent and hardware implementation, employing a hybrid strategy that includes C++ software testing, C/RTL co-simulation, and traditional SystemVerilog/ Universal Verification Methodology (UVM) testbenches to guarantee equivalence and compliance. Your role demands comprehensive ownership of the verification life-cycle, from architectural planning and mixed-abstraction debugging to final coverage closure, while continuously refining methodologies to handle the specific complexities of HLS-based silicon design.

Responsibilities

• Lead comprehensive verification strategies and signoff for complex blocks where the source is C/C++, taking full ownership of quality from HLS code to generated RTL.
• Design and maintain advanced environments, including C/C++ GoogleTest for functional validation and SystemVerilog/UVM for RTL timing and system interactions.
• Employ HLS-specific methods such as C/RTL co-simulation, formal equivalence verification, and transaction-level modeling to ensure hardware fidelity.
• Drive complex bug hunting and coverage analysis across both C++ and RTL domains to ensure complete verification of the design transformation.
• Partner with design teams to optimize C++ code for verifiability and mentor junior engineers on the nuances of HLS verification.

Requirements & Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with Design Verification.
• Experience with SystemVerilog and Universal Verification Methodology (UVM).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Practical experience with High-Level Synthesis tools (e.g., Catapult, Vivado, XLS) and strong C/C++ skills for developing HLS testbenches and models.
• Expertise in video processing, image pipelines, or video compression standards such as AV1, AV2, or H.264.
• Demonstrated ability to debug complex issues across C/C++ and RTL levels using industry-standard EDA tools like VCS, Xcelium, or Verdi.

Application Instructions

Apply directly on Google Careers at Senior Silicon Design Verification Engineer, YouTube Video Accelerators↗.

Direct application sign-in: Submit Application↗

Note: In most instances, this position requires in-person interviews as part of the hiring process.