- Location
- Nashua, NH, United States · Remote
- Compensation
- $130K - $155K*
- Employment
- Not stated
- Experience level
- STAFF (10+ years exp)
- Specialization
- Senior Principal II FPGA Design Engineer, TheLadders
- Source
- TheLadders
Job Description Electronic Combat Solutions Hardware Engineering Group is seeking a Senior Principal II FPGA Design Engineer to lead and develop a team of FPGA designer engineers through all phases of development. The ideal candidate is expected to perform activities including requirements generation and design architecture; technical oversight and mentoring of team members; as well as ownership of RTL coding, synthesis, basic test bench development, lab testing, and product support. As this job requires a government clearance of secret or higher, the position requires full-time onsite presence. This position will be posted for at least 5 calendar days. The posting will remain active until the position is filled, or a qualified pool of candidates is identified. Required Skills and Education 10+ years of relevant experience with bachelor's degree (less with an advanced degree) Current Security Clearance (Secret), or eligible to obtain one Ability to distill higher level requirements into micro-architecture Extensive experience in FPGA (preferred) or ASIC Design / Development Experience leading a design team Proficient in VHDL (preferred) or Verilog HDL coding Familiarity with Xilinx Vivado/ISE or Altera Quartus Digital simulation using Modelsim/Questa Strong understanding of timing driven design including clock domain crossing circuitry Strong lab debug and problem solving skills Strong written and oral communication skills Ability to mentor and willingness to be mentored Experience with high-speed interfaces like PCIe, SerDes, ADC/DAC, DDR3/4 Familiarity with revision control (GIT, CVS, Clearcase, Subversion, etc.) Knowledgeable in Tcl/Tk and UNIX/Linux shell programming Preferred Skills and Education Active Security Clearance (Secret) Experience with DSP fundamentals and FPGA implementation Proficient in C/C++, Perl, Python programming Experience with Matlab/Simulink Experience creating unique designs and supporting legacy designs Experience with UVM/System Verilog
- 10+ years of relevant experience with bachelor's degree (less with an advanced degree)
- Current Security Clearance (Secret), or eligible to obtain one
- Ability to distill higher level requirements into micro-architecture
- Extensive experience in FPGA (preferred) or ASIC Design / Development
- Experience leading a design team
- Proficient in VHDL (preferred) or Verilog HDL coding
- Familiarity with Xilinx Vivado/ISE or Altera Quartus
- Digital simulation using Modelsim/Questa
- Strong understanding of timing driven design including clock domain crossing circuitry
- Strong lab debug and problem solving skills
- Strong written and oral communication skills
- Ability to mentor and willingness to be mentored
- Experience with high-speed interfaces like PCIe, SerDes, ADC/DAC, DDR3/4
- Familiarity with revision control (GIT, CVS, Clearcase, Subversion, etc.)
- Knowledgeable in Tcl/Tk and UNIX/Linux shell programming
- Active Security Clearance (Secret)
- Experience with DSP fundamentals and FPGA implementation
- Proficient in C/C++, Perl, Python programming
- Experience with Matlab/Simulink
- Experience creating unique designs and supporting legacy designs
- Experience with UVM/System Verilog